The present invention relates generally to a pulse delay circuit that delays edges of an input pulse train and more specifically to a pulse delay circuit for geneting a high speed jittered test signal.
Digital circuits in electric instruments process a plurality of pulses of a pulse train that may not be ideal due to phase variations in the leading and/or trailing edges of the pulses due to outside noise or the like. The phase variations in the leading and/or trailing edges of pulses in a pulses train is referred to in the electronics industry as jitter. Therefore, digital circuits need to be designed to work in the presence of jitter on the leading edges and/or trailing edges of the pulses. It is desirable to inspect a prototype circuit by providing a jittered pulse train to the circuit to confirm that it works in the presence of a jittered signal. This inspection is called a jitter tolerance test.
For a jitter tolerance test, a jittered test signal (pulse train) is necessary. The jittered test signal is produced by inducing jitter to the leading and/or the training edges of a normal pulse train (called a reference pulse train hereinafter). The jittered est signal is then provided to the digital circuit under test. The jitter tolerance test is performed by comparing the jittered pulse train to the normal pulse train. To induce jitters to the leading and/or trailing edges, delays are provided to the desired edges of the reference pulse train and then the delays are continuously changed.
Japanese patent publication No. 2004-236279 corresponding to US Publication No. 2004/0135606 discloses a prior art example of a jitter addition circuit. The jitter addition circuit receives a reference pulse train which is alternately coupled to two delay blocks. Each delay block has a pulse delay circuit receiving delay values which provide delays to the leading and/or training edges of the reference pulse train. The delay values of each pulse delay circuit are changed while the delay block is not receiving the pulse train. The delay values of the pulse delay circuits are changed so that the leading and/or training edges output pulse train can contain various levels of jitter.
FIG. 1 shows a block diagram of the pulse delay circuit in each of delay blocks and FIG. 2 shows a timing chart of the waveforms that the circuit provide. A buffer 10 receives a reference pulse train and provides non-inverted and inverted output pulse train outputs to low pass filters (LPF) 12 and 14. The LPFs 12 and 14 remove high frequency components of the non-inverted and inverted pulse trains resulting in the pulses having ramping leading and trailing edges. Comparators 16 and 18 receive the ramped pulses of the pulse trains from the LPFs 12 and 14 and compare them with the respective reference voltages VREF1 and VREF2. The resulting output pulse trains from the comparators 16 and 18 have modified edge positions relative to the reference pulse train as shown in FIGS. 2d and 2e. The LPFs 12 and 14 and comparators 16 and 18 work as delay means. One-shot pulse circuits 20 and 22 convert the pulses from the comparators 16 and 18 into one-shot pulses. This prevents both the S and R input pulses to an SR flip-flop 24 from becoming high at the same time to prevent the SR flip-flop 24 from becoming unstable.
The reference voltages VREF1 and VREF2 control the leading edge positions of the one-shot pulses from the one-shot pulse circuits 20 and 22. The leading edge of the one-shot pulses from the one-shot pulse circuit 20 determines the leading edge positions of the pulses from the Q output of the SR flip-flop 24 and the leading edge of the one-shot pulses from the one-shot pulse circuit 22 determines the trailing edge positions of the pulses from the Q output of the SR flip-flop 24 . Therefore, continuous variations of the reference voltages VREF1 and VREF2 lead to continuous position changes of the edges of the output pulse of the SR flip-flop 24, which provides a pulse train having jitter relative to the input reference pulse train.
As described, the voltages VREF1 and VREF2 change the timing of the edges of the two one-shot pulses provided to the S and R inputs of the SR flip-flop 24. This timing is changing during the jitter being induced so that the one-shot pulses must be controlled so as not to overlap to prevent the S and R inputs from being high at the same time. The SR flip-flop also has setup and hold times which must be considered. That is, the setup and hold times of the SR flip-flop and the pulse width of the one shot pulse restrict a margin of the jitter. Therefore, what is desired is to widen the jitter margin and induce larger jitter to a faster input pulse train.